1. Field of the Invention
The present invention relates to a bias circuit of a single-ended push-pull circuit, and more particularly to a bias circuit capable of eliminating the switching and cross-over distortions of power transistors in Class B operation.
2. Prior Art
Though Class B amplifiers have higher efficiency than that of Class A amplifiers, the former were disadvantageous in that the so-called switching distortion is caused following a switching operation of bipolar transistors because the bipolar transistors are cut off in their non-operation state.
Referring to FIG. 1, the switching distortion will be now described in the case where the conventional single-ended push-pull circuit is operated in Class B mode. The single-ended push-pull circuit comprises a complementary circuit of NPN and PNP transistors, in which plural power transistors (three in FIG. 1) are connected with each other in Darlington manner. Connected in series between the bases of first stage NPN and PNP transistors Q.sub.5 and Q.sub.6 are a diode D for thermal compensation and a variable resistance VR for voltage adjustment, and supplied to this in-series circuit is current from a constant current circuit CS to form a bias circuit for the single-ended push-pull circuit. For the purpose of suppressing minimum the switching distortion even when such single-ended push-pull circuit is operated in Class B mode, the voltage between the bases of transistors Q.sub.5 and Q.sub.6 is determined to become similar to Class AB operation by adjusting the variable resistance VR in such a way that small current is caused to flow through output stage power transistors Q.sub.1 and Q.sub.2 when no input signal is present, that is, when the state is quiescent.
In this single-ended push-pull circuit of Class B mode, potential difference is almost not caused across an emitter resistance R.sub.1 or R.sub.2 since current flowing through the resistance R.sub.1 or R.sub.2 of output stage power transistor Q.sub.1 or Q.sub.2 is small in the quiescent state. However, potential difference is caused across the emitter resistance R.sub.1 or R.sub.2 since large current flows through the resistance R.sub.1 or R.sub.2 at the time of signals being applied as inputs. For example, providing that the NPN transistor Q.sub.1 is operated and that an output signal current I.sub.O is flowing through the resistance R.sub.1, a potential difference of I.sub.O R.sub.1 is caused. In addition, large current flows even through the power transistor Q.sub.1 to increase the voltage V.sub.BE between its base and emitter. Thus, the potential difference between the base of first stage NPN transistor Q.sub.5 and an output point (or between a and O) is increased. On the other hand, since the potential difference between the bases of first stage NPN and PNP transistors Q.sub.5 and Q.sub.6 (or between a and b) is determined to a certain value by the bias circuit, the bias voltage between the base of first stage PNP transistor Q.sub.6 and the output point (or between b and O) becomes insufficient and the potential difference therebetween becomes zero or reversed causing the PNP transistor Q.sub.2 to be cut off. As the result, the base carrier of bipolar PNP transistor Q.sub.2 is ejected, but this ejection of base carrier is not performed instantly but with a time delay, thus causing distortion in the wave form of output signals. Even in the case where input signals to the push-pull circuit are reversed and the bipolar PNP transistors Q.sub.2 is returned to operation, the injection of base carrier is also performed with a time delay causing distortion in the wave form of output signals. In short, it is impossible to avoid the occurrence of switching distortion as long as the biased state is caused under which PNP transistors Q.sub.2, Q.sub.4 and Q.sub.6 are cut off. Similarly, the switching distortion also arises in the case where NPN transistors Q.sub.1, Q.sub.3 and Q.sub.5 are cut off.
It is therefore conceived to prevent the occurrence of such switching distortion that current flowing through the output stage of push-pull circuit is detected to control the voltage between the bases of input stage transistors and to compensate for the shortage of bias voltage at the time of signals being applied as inputs, preventing the output transistors from being cut off.
Basing on this concept, a bias circuit shown in FIG. 2 was proposed. Also in this circuit the variable resistance VR is adjusted to cause bias current to flow through output stage transistors Q.sub.1 and Q.sub.2 in the quiescent state. When an input signal e is impressed through the transistor Q.sub.7 and the NPN transistor Q.sub.1 is operated, for example, a potential difference arises across the resistance R.sub.1, and V.sub.BE of power transistor Q.sub.1 also increases. The potential difference between a and O increases by a value corresponding to the increase of potential difference between both terminals of resistance R.sub.1 and that of V.sub.BE. Therefore, the potential difference between the base of transistor Q.sub.10 and the point a increases by a value corresponding to the sum of these increases, so that current flows through the resistance R.sub.3 and a potential difference corresponding to this sum of increases appears in the resistance R.sub.3. The voltage between emitter and collector of transistor Q.sub.8 therefore increases by a value corresponding to the potential difference between both terminals of resistance R.sub.3 and the potentail difference between a and b increases by a value corresponding to the increase of this voltage. Accordingly, the PNP transistor Q.sub.2 is biased to allow bias current to flow therethrough even at the time of signals being applied as inputs as well as at the time of no signal present. When the input signal is reversed and the PNP transistor Q.sub.2 is operated, a potential difference appears between both ends of resistance R.sub.4 corresponding to the increase of potential difference in the resistance R.sub.2 and that of V.sub.BE of power transistor Q.sub.2, and the voltage between emitter and collector of transistor Q.sub.9 increases by a value corresponding to the sum of these increases, so that the bias voltage between a and b increases and bias current is caused to flow through the NPN transistor Q.sub.1 similarly as at the time of no signal present. Therefore, power transistors Q.sub.1 and Q.sub.2 are not held cut off to thereby prevent the switching distortion from being occurred.
However, the circuit shown in FIG. 2 employs constant voltage sources E.sub.1 and E.sub.2. Therefore, the circuit practically used becomes complicated and is intended only to attain positive feedback operation in which the increase of potential difference of operating output stage transistors is detected to increase the voltage of bias circuit. When the bias voltage of unoperating transistors decreases, no change in voltage appears in the collector of the transistor Q.sub.8 and the voltage of bias circuit cannot be increased because constant voltage sources E.sub.1 and E.sub.2 are used to form reference voltages and their internal resistances do not change. Namely, since negative feedback operation is not attained by the circuit, it may happen that the unoperating transistor Q.sub.2 is cut off when the bias voltage of unoperating transistors decreases, thus making it impossible to completely remove the switching distortion.
Further, in the circuit shown in FIG. 2, the emitters of transistors Q.sub.10 and Q.sub.11 are respectively connected through resistances R.sub.3 and R.sub.4 to the bases of first stage transistors Q.sub.5 and Q.sub.6 of push-pull circuit. This means that transistors Q.sub.10 and Q.sub.11 serve as loads for the previous voltage amplification stage. Generally, the emitter of transistor has low impedance and non-linearity characteristic, and the output impedance of voltage amplification stage is the highest in the amplifying device. Since the emitter of transistor Q.sub.10 having low impedance is connected to the voltage amplification stage of high impedance in the circuit shown in FIG. 2, these matters that the load of voltage amplification stage becomes low and that the emitter of transistor Q.sub.10 has non-linearity characteristic contribute therefore to the occurrence of distortion.
Furthermore, since transistors Q.sub.8 and Q.sub.10 and transistors Q.sub.9 and Q.sub.11 are connected with each other in inverted Darlington manner in the circuit shown in FIG. 2, the paired may be regarded as an NPN transistor and a PNP transistor, respectively, where the emitters of equivalent NPN and PNP transistors are arranged to connect to points a and b, respectively. Even if basing on this concept, the circuit shown in FIG. 2 causes distortion because a low load of non-linearity is connected to the voltage amplification stage.
Japanese Patent Pre-Publication No. 54-77054 discloses a circuit shown in FIG. 3. The emitters of controlling transistors Q.sub.12 and Q.sub.13 are also connected to the points a and b, respectively, in this circuit, thus making it impossible to avoid the occurrence of distortion due to the fact that the load of voltage amplification stage becomes low similarly as in the conventional circuit shown in FIG. 2. In addition, the potential difference appearing in the both terminals of emitter resistance R.sub.1 or R.sub.2 of output stage transistor Q.sub.1 or Q.sub.2 is applied as input to between the base and emitter of controlling transistor Q.sub.12 or Q.sub.13 in the circuit shown in FIG. 3, so that the potential difference is amplified to greatly increase the bias voltage between a and b. The increase of bias voltage between a and b does not correspond in relation of 1 to 1 to that of potential difference between a and O or b and O, thus making it impossible to attain accurate bias control.
A circuit shown in FIG. 4 was disclosed in U.S. Pat. No. 3,995,228, in which operation is attained in such a way that output transistors Q.sub.1 and Q.sub.2 are not cut off by connecting two V.sub.BE Multipliers in series and letting the constant voltage source E.sub.3 or E.sub.4 and the diode D.sub.3 or D.sub.4 form a reference voltage. However, voltage sources E.sub.3, E.sub.4 of low impedance and diodes D.sub.3, D.sub.4 of non-linearity are connected through resistances R.sub.6 and R.sub.7 to the points a and b of final voltage amplification stage of circuit which is operated in high impedance. As the result, a load of low impedance and non-linearity is connected to the voltage amplification stage, to thereby cause distortion similarly as in the circuits shown in FIGS. 2 and 3. In addition, since constant voltage sources E.sub.3 and E.sub.4 are used in the circuit, negative feedback is not attained to increase the bias voltage between a and b when the transistors Q.sub.1 and Q.sub. 2 are about to be cut off.